PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32 Copyright (c) 1998 H.Oda! [COMMENT]=Author Howard Chu hyc@highlandsun.com [MODEL]=82855 [VID]=8086:Intel [DID]=3340:Host-HI Bridge (00)=Vendor Identification (01)=Vendor Identification (02)=Device Identification (03)=Device Identification [04:7]=Address/Data Stepping (Not implemented) [04:6]=Parity Error Enable (Not implemented) [04:5]=VGA Palette Snoop (Not implemented) [04:4]=Memory Write/Invalidate 0=hardwired to 0 [04:3]=Special Cycle Enable 0=hardwired to 0 [04:2]=Bus Master Enable 1=hardwired to 1 [04:1]=Memory Access Enable 1=hardwired to 1 [04:0]=I/O Access Enable 0=hardwired to 0 [05:1]=Fast Back-to-Back (Not implemented) [05:0]=SERR# Enable 1=enable 0=disable [06:7]=Fast Back-to-Back 1=hardwired to 1 [06:4]=Capability List 1=enabled [07:6]=Signaled System Error Status 1=asserted SERR# [07:5]=Received Master Abort Status 1=abort happened [07:4]=Received Target Abort Status 1=abort happened [07:3}=Signaled Target Abort Status 0=hardwired to 0 [07:2]=DEVSEL# Timing[1:0] 00=hardwired to 0 [07:1]=(Same as bit2) [07:0]=Data Parity Detected (Not implemented) (08)=Revision Identification 03h=A3 Stepping 21h=B1 Stepping (0A)=Sub-Class Code 00h=Host Bridge (0B)=Base Class Code 06h=Bridge Device (0D)=Master Latency Timer 00h=hardwired to 00h (0E)=Header Type 00h=hardwired to 00h [10:7]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB [10:6]=(Same as top) [10:5]=(Same as top) [10:4]=(Same as top) (10:3)=Prefetchable 1=hardwired to 1 (10:2)=Type[1:0] 00=hardwired to 00 (10:1)=(Same as bit2) (10:0)=Memory Space Indicator 0=hardwired to 0 [11]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB [12:7]=Lower Programmable Base Address[1:0] [12:6]=(Same as top) [12:5]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB [12:4]=(Same as bit5) [12:3]=(Same as bit5) [12:2]=(Same as bit5) [12:1]=(Same as bit5) [12:0]=(Same as bit5) [13:7]=Upper Programmable Base Address[3:0] [13:6]=(Same as top) [13:5]=(Same as top) [13:4]=(Same as top) [13:3]=Lower Programmable Base Address[3:0] [13:2]=(Same as bit3) [13:1]=(Same as bit3) [13:0]=(Same as bit3) [14:7]=15[3]:14[4] hardwired to 0 forces SMSIZE 4KB [14:6]=(Same as top) [14:5]=(Same as top) [14:4]=(Same as top) (14:3)=Prefetchable 0=hardwired to 0 (14:2)=Type[1:0] 00=hardwired to 00 (14:1)=(Same as bit2) (14:0)=Memory Space Indicator 0=hardwired to 0 [15:7]=Upper Programmable Base Address[3:0] [15:6]=(Same as bit7) [15:5]=(Same as bit7) [15:4]=(Same as bit7) [15:3]=15[3]:14[4] hardwired to 0 forces SMSIZE 4KB [15:2]=(Same as bit3) [15:1]=(Same as bit3) [15:0]=(Same as bit3) [16]=Upper Programmable Base Address[11:4] [17]=Upper Programmable Base Address[19:12] [2C]=Subsystem Vendor ID(Lo) defaults 00h, write once [2D]=Subsystem Vendor ID(Hi) defaults 00h, write once [2E]=Subsystem ID(Lo) defaults 00h, write once [2F]=Subsystem ID(Hi) defaults 00h, write once [34]=Capabilities Pointer E4h=hardwired to E4h [51:1]=Aperture Access 1=enable 0=disable [5C]=DQSMRG(Lo) [5D:4]=DQSMRG(Hi)[4:0] maximum is 07h [5D:3]=default is 2Fh [5D:2]=(Same as bit4) [5D:1]=(Same as bit4) [5D:0]=(Same as bit4) [60]=DRAM Row Boundary Addr 0 32MB increments [61]=DRAM Row Boundary Addr 1 [62]=DRAM Row Boundary Addr 2 [63]=DRAM Row Boundary Addr 3 [70]=DRAM Row Attribute 0,1 001=2KB 010=4KB [71]=DRAM Row Attributr 2,3 011=8KB 100=16KB [78:5]=CAS# Latency[5:4] 00=2.5 01=2 [78:4]=(Same as bit5) 10=1.5 11=(Reserved) [78:2]=DRAM RAS# to CAS# Delay 0=3 DCLK 1=2 DCLK [78:0]=DRAM RAS# Precharge 0=3 DCLK 1=2 DCLK [79:3]=DQS Slave DLL Dynamic 1=idle down 0=always on [79:2]=tRAS[2:1] 00=7 clocks 01=6 clocks [79:1]=(Same as bit2) 10=5 clocks 11=(Reserved) [7A:3]=No wait for DDR closes 0=close 1=no close [7A:2]Page Close Counter[2:0] 000=no close 001=4-7clks [7A:1](Same as bit2) 010=8-15 011=16-31 100=64-127 [7A:0](Same as bit2) 101=128-255 110=192-383 111=255-510 [7B:7]=Add CKE to CS Clk R/W 1=add a cycle [7B:6]=Add CKE to CS Pre/Act 1=add a cycle [7B:5]=Back to Back Write-Read 1=recommended [7B:4]=Back to Back Read-Write 0=CL2.5 1=CL1.5,CL2 [7B:3]=Back to Back Read 1=recommended [7B:2]=tRD[2:0] 000=9 DCLK 001=8 010=7 [7B:1]=(Same as bit2) 011=6 100=5 101=4 [7B:0]=(Same as bit2) 110=3 others=(Reserved) [7C:6]=Mode Select[6:4] 000=post-reset 001=NOP [7C:5]=(Same as bit6) 010=Precharge 011=Mode Reg Set [7C:4]=(Same as bit6) 100=XMode Reg 110=CBR 111=Normal [7C:0]=DRAM type 1=DDR SDRAM [7D:5]=Dynamic CS disable 1=tristate 0=always driven [7D:4]=SM I/F Tristate Enable 1=tristate [7D:2]=Refresh Mode Select[2:0] 000=disabled 001=15.6sec [7D:1]=(Same as bit2) 010=7.8sec 011=64sec [7D:0]=(Same as bit2) Other=(Reserved) [7E:7]=Reduced Command Drv Dly 0=2 clk 1=3 clk [7E:6]=Reduced Command Drv Ena 0=default 1=enabled [7E:5]=DRAM Integrity Mode 0=Non-ECC 1=ECC [7E:3]=DRB Granularity[3:2] 00=DRB reg uses 32MB units [7E:2]=(Same as bit3) Other=(Reserved) [7E:0]=Disable SCK Tristate 0=tristate 1=drive low [7F:7]=Revision Number[7:6] 00=Revision 00 [7F:6]=(Same as bit7) [7F:5]=Init Complete 1=DRAM array initialized [7F:4]=Dynamic PowerDown Ena 0=disable 1=enable [80:7]=RCVEN/RDCLK 81[0]:80[4] [80:6]=(Same as bit7) [80:5]=(Same as bit7) [80:4]=(Same as bit7) [80:3]=RCVEN/RDCLK timing[3:2] 00=5.0/3.75/3.0 01=7.5/5.625/4.5 [80:2]=(Same as bit3) 10=10.0/7.5/6.0 11=12.5/9.375/7.5ns [80:1]=RCVEN/RDCLK timing[1:0] 00=1clk(10/7.5/6.0ns) [80:0]=(Same as bit1) 01=2clk (20/15/12ns) 10=3clk(30/22.5/18ns) [81:0]=RCVEN/RDCLK 81[0]:80[4] [82]=DRAM Opportunistic Refresh 80h=default [83]=DQS Control 0Ah=default [84]=ECC bit invert vector [85:7]=ECC diagnostic enable 1=enable bit invert (86)=DRAM Error Syndrome (87:3)=DRAM Error Status[3:2] 00=1st Quad 01=2nd Quad (87:2)=(Same as bit3) 10=3rd Quad 11=4th Quad (87:1)=Error Type 0=single, no error 1=multi-bit (87:0)=Error Occurred 0=No ECC Errors 1=At least one (8C)=Error Address Pointer (8D)=Error Address Pointer (8E)=Error Address Pointer (8F)=Error Address Pointer [90:5]=PAM[0] Write Enable 0F0000h - 0FFFFFh [90:4]=PAM[0] Read Enable 0F0000h - 0FFFFFh [91:5]=PAM[1] Write Enable 0C4000h - 0C7FFFh [91:4]=PAM[1] Read Enable 0C4000h - 0C7FFFh [91:1]=PAM[1] Write Enable 0C0000h - 0C3FFFh [91:0]=PAM[1] Read Enable 0C0000h - 0C3FFFh [92:5]=PAM[2] Write Enable 0CC000h - 0CFFFFh [92:4]=PAM[2] Read Enable 0CC000h - 0CFFFFh [92:1]=PAM[2] Write Enable 0C8000h - 0CBFFFh [92:0]=PAM[2] Read Enable 0C8000h - 0CBFFFh [93:5]=PAM[3] Write Enable 0D4000h - 0D7FFFh [93:4]=PAM[3] Read Enable 0D4000h - 0D7FFFh [93:1]=PAM[3] Write Enable 0D0000h - 0D3FFFh [93:0]=PAM[3] Read Enable 0D0000h - 0D3FFFh [94:5]=PAM[4] Write Enable 0DC000h - 0DFFFFh [94:4]=PAM[4] Read Enable 0DC000h - 0DFFFFh [94:1]=PAM[4] Write Enable 0D8000h - 0DBFFFh [94:0]=PAM[4] Read Enable 0D8000h - 0DBFFFh [95:5]=PAM[5] Write Enable 0E4000h - 0E7FFFh [95:4]=PAM[5] Read Enable 0E4000h - 0E7FFFh [95:1]=PAM[5] Write Enable 0E0000h - 0E3FFFh [95:0]=PAM[5] Read Enable 0E0000h - 0E3FFFh [96:5]=PAM[6] Write Enable 0EC000h - 0EFFFFh [96:4]=PAM[6] Read Enable 0EC000h - 0EFFFFh [96:1]=PAM[6] Write Enable 0E8000h - 0EBFFFh [96:0]=PAM[6] Read Enable 0E8000h - 0EBFFFh [97:7]=Fixed DRAM Hole Cntl 0=none 1=15-16MB [9D:6]=SMM Space Open [9D:5]=SMM Space Closed [9D:4]=SMM Space Locked [9D:3]=Global SMRAM Enable (9D:2)=Compatible SMM Space Base[2] 010=A0000h - BFFFFh (9D:1)=(Same as bit2) (9D:0)=(Same as bit2) [9E:7]=H_SMRAM_EN (H_SMRAME) [9E:6]=E_SMRAM_ERR (E_SMERR) [9E:5]=SMRAM_Cache (SM_CACHE) forced to 1 [9E:4]=SMRAM_L1_EN (SM_L1) forced to 1 [9E:3]=SMRAM_L2_EN (SM_L2) forced to 1 [9E:2]=TSEG_SZ[1:0] (T_SZ)[1:0] 0=128,1=256,10=512,11=1M [9E:1]=(Same as bit2) [9E:0]=TSEG_EN (T_EN) 1=enable SMRAM 0=disable (A0)=AGP Capability ID (A1)=Next Capability Pointer (A2:3)=Minor AGP Revision Number[3:0] (A2:2)=(Same as bit3) (A2:1)=(Same as bit3) (A2:0)=(Same as bit3) (A2:7)=Major AGP Revision Number[3:0] (A2:6)=(Same as top) (A2:5)=(Same as top) (A2:4)=(Same as top) (A4:5)=AGP Greater than 4GB 0=not supported (A4:4)=AGP Fast Writes 1=supported (A4:2)=AGP Data Rates[2:0] 1=supports 4x (A4:1)=(Same as bit2) 1=supports 2x (A4:0)=(Same as bit2) 1=supports 1x (A5:1)=AGP Side Band Addressing 1=supported (A7)=AGP Maximum Request QueueDepth 1fh=default 32 max [A8:4]=AGP Fast Write Enable 1=enable 0=disable [A8:2]=AGP Data Transfer Rate[2] 100=4x [A8:1]=AGP Data Transfer Rate[1] 010=2x [A8:0]=AGP Data Transfer Rate[0] 001=1x [A9:1]=AGP Side Band Enable 1=enable 0=disable [A9:0]=AGP Enable 1=enable 0=disable [B0:7]=GTLB Enable (and GTLB Flush Control) [B4:5]=Graphics Aperture Size (APSIZE) 000000=256MB [B4:4]=Graphics Aperture Size 100000=128MB [B4:3]=Graphics Aperture Size 110000=64MB [B4:2]=Graphics Aperture Size 111000=32MB [B4:1]=Graphics Aperture Size 111100=16MB [B4:0]=Graphics Aperture Size 111110=8MB 111111=4MB [B9:7]=Aperture Translation Table Base [15:12] [B9:6]=(Same as top) [B9:5]=(Same as top) [B9:4]=(Same as top) [BA]=Aperture Translation Table Base [23:16] [BB]=Aperture Translation Table Base [31:24] [BC]=AGP Multi-Trans Timer x8 66MHz clocks [BD]=AGP LowPrio Trans Timer x8 66Mhz clocks [C4]=Top of Low Memory(Lo) [C5]=Top of Low Memory(Hi) [C6:5]=MDA Present [C6:2]=In-Order Queue Depth 0=1 1=12 [C7:3]=Memory Frequency Sel[3:2] 00=200MHz 10=266MHz [C7:2]=(Same as bit3) 01=333MHz 11=(Reserved) [C8:6]=SERR on Hub I/F A Target Abort [C8:5]=Unimplemented Hub I/F Special Cycle [C8:4]=AGP Access Outside of Graphics Aperture [C8:3]=Invalid AGP Access [C8:2]=Invalid AGP Aperture Translation Table Entry [C8:1]=Multiple-bit DRAM ECC Error [C8:0]=Single-bit DRAM ECC Error [C9:7]=DRAM Read Throttle Flag [C9:6]=DRAM Write Throttle Flag [C9:3]=Catastrophic Thermal Sensor Event [C9:2]=Hi/Lo Thermal Sensor Event [C9:1]=LOCK to non-DRAM Memory [C9:0]=PSB Address above TOM [CA:6]=SERR on Target Abort [CB:7]=SERR on DRAM Read Throttle [CB:6]=SERR on DRAM Write Throttle [CB:3]=SERR on Catastrophic Thermal Sensor Event [CB:2]=SERR on Hi/Lo Thermal Sensor Event [CB:1]=SERR on Non-DRAM LOCK [CB:0]=SERR on PSB access above TOM [CC:1]=SMI on Multiple-bit ECC Error [CC:0]=SMI on Single-bit ECC Error [CD:7]=SMI on DRAM Read Throttle [CD:6]=SMI on DRAM Write Throttle [CD:3]=SMI on Catastrophic Thermal Sensor Event [CD:2]=SMI on Hi/Lo Thermal Sensor Event [CE:1]=SCI on Multiple-bit ECC Error [CE:0]=SCI on Single-bit ECC Error [CF:7]=SCI on DRAM Read Throttle [CF:6]=SCI on DRAM Write Throttle [CF:3]=SCI on Catastrophic Thermal Sensor Event [CF:2]=SCI on Hi/Lo Thermal Sensor Event [DC:3]=Spatial Flush Mask[3:2] 00=4k or less 01=8k [DC:2]=(Same as bit3) 10=(Reserved) 11=16k [DC:1]=Spatial Flush Mode[1:0] 00=Page Hit 01=Row Miss [DC:0]=(Same as bit1) 10=(Reserved) 11=disabled [DE]=Scratchpad(Lo) [DF]=Scratchpad(Hi) (E4)=CAP_ID 05h=vendor dependent (E5)=Next Capability Pointer A0h=point to AGP CAPID (E6)=CAPID Length 04h=struct len = 4 bytes (E7:7)=DDR Capability 1=200/266MHz 0=200/266/333 (E7:6)=Mobile Power Mgmt 1=supported [F4:1]=Device #6 Enable 1=enable 0=disable [F6:6]=SM MMR Enable 1=enable 0=disable